The invention relates to integrated circuits, and more particularly, to a FAMOS memory cell or a memory cell based on a FAMOS transistor.
Floating gate avalanche injection MOS (FAMOS) technology uses a memory cell that includes a PMOS transistor whose single gate is isolated, that is, not electrically connected. The single gate is therefore floating.
This memory cell can be obtained without adding additional steps to the basic technological process for fabricating a PMOS transistor. Unlike other memory cells, for example FLASH, EPROM or EEPROM memory cells, which have a floating gate and a control gate, the FAMOS memory cell has only a floating gate.
It is not possible to electrically erase a FAMOS memory cell. Ultraviolet radiation must be used to erase a FAMOS memory cell. This type of memory cell is therefore more particularly used in a one time programmable (OTP) memory.
In view of the foregoing background, an object of the present invention is to avoid erasing by ultraviolet radiation so that a FAMOS memory cell can be programmed and erased several times, that is, a memory cell that includes a PMOS transistor with a single floating gate, integrated into an integrated circuit.
This and other objects, advantages and features according to the present invention are provided by electrically erasing a FAMOS memory cell. The invention therefore goes against current technology, and as a result, a FAMOS memory cell may be used as a non-volatile EEPROM or FLASH memory cell.
In one embodiment of the invention, the memory cell can be erased regardless of the voltages on the source and the drain of the PMOS transistor, provided that there is applied to the substrate a voltage having a value at least 4 volts higher than the lower of the voltages applied to the source and the drain. However, the substrate voltage must remain below a predetermined limit voltage, above which the memory cell may be destroyed.
For example, the predetermined limit voltage is the breakdown voltage of the substrate/source and substrate/drain diodes. Of course, this predetermined limit voltage, above which the memory cell may be destroyed, is based upon the technology used. At present this predetermined limit voltage is set at about 10 volts.
To reduce the time needed to erase the memory cell, a voltage can advantageously be applied to the substrate whose value is at least 6 volts higher than the lower of the voltages applied to the source and the drain. For example, to obtain an erasure time on the order of 1 minute, substrate voltages on the order of 7 to 8 volts are applied, for example. The same voltage can be applied to the source and the drain.
However, another way to reduce the erasure time is to apply a non-zero positive voltage difference between the source and the drain. With this being so, in some applications, it is preferable for the value of the difference between the source voltage and the drain voltage to remain below a predetermined threshold, so as not to place the memory cell in an intermediate electrical state. For example, a predetermined threshold value less than 2 volts, for example, on the order of 1 volt, can advantageously be used.
Instead of this, it would be equally possible to apply a variable voltage difference between the source and the drain. For example, at the start of the erase phase a positive voltage difference could be applied between the source and the drain to begin erasing faster, after which a zero voltage difference would be applied between the source and the drain to avoid an intermediate electrical state of the memory cell.
The memory cell according to the invention can be erased electrically regardless of the configuration of the PMOS transistor of the memory cell. Thus, the PMOS transistor can have a conventional linear configuration, or an annular configuration including an electrode at the center surrounded by the gate and a peripheral electrode. For some types of process, the annular configuration makes erasure more efficient by reducing the necessary erase time compared to a linear configuration.
The invention also provides a memory device including a FAMOS memory cell. According to one general feature of the invention, the memory cell is electrically erasable. In one embodiment of the invention, the memory cell includes a PMOS transistor in a semiconductor substrate, and the device includes erasing means adapted to apply to the substrate a voltage having a value at least 4 volts higher than the lower of the voltages applied to the source and to the drain, and less than a predetermined limit value above which the cell may be destroyed.
In a preferred embodiment of the invention, the erasing means apply a voltage to the substrate whose value is at least 6 volts higher than the lower of the voltages applied to the source and to the drain. To reduce the erase time, the erasing means are advantageously apply a non-zero positive voltage difference between the source and the drain, preferably less than a predetermined threshold value, for example, on the order of 1 volt.
The memory device according to the invention also includes programming means for writing data in the memory cell, reading means for reading the content of the memory cell, and control means for connecting the programming, reading and erasing means selectively to the memory cell as a function of the mode of operation used.
The device may further include a plurality of electrically erasable FAMOS memory cells, for example, a memory array formed by a matrix of memory cells organized in rows and columns. The invention also provides an integrated circuit including a memory device as defined above.